PURPOSE : To reduce a chip use area and to minimize the number of pieces of shift register latches by sharing a piece of serial latch with between two pairs of folded bit lines from two arrays of a memory cell. CONSTITUTION : A first class multiplex device 14 selects one side pair between two pairs of folded bit lines from the array 10, and a second class multiplex device 24 selectively connects the other pair between two pairs of folded bit line pair from the array 24 to the serial latch 100 for accessing to a parallel port or a serial port 60, 70. Then, unlimited vertical scrolling becomes possible by using a copy mode capable of simultaneously executing in two operational cycles, and masked write-in is facilitated, and simultaneously, complication in clocking is reduced. Thus, the chip use area is reduced, and the number of pieces of shift register latches are reduced.