The elevator absolute sync. position detecting circuit in an elevator position detecting circuit for controlling a chip selection of a first parallel data adapter in response to an output signal of a first decoder for decoding an address signal of a first CPU, connecting a data bus between the first parallel data adapter and first CPU as well as a data bus between the first parallel data adapter and a second parallel data adapter, controlling a chip selection of the second parallel data adapter, a timer and a RAM connected to a backup battery by means of an output signal of a second decoder to receive/supply the data from them includes a decoder for decoding the address signal of the first CPU, magnet switches for generating a signal in accordance with the position of an elevator, and signal input ports subjected to the chip selection control by an output signal of the third decoder for receiving output signals from the magnet switches to supply the inputs to the first CPU.