A programmable logic device (PLD) is disclosed which can efficiently, in a real estate sense, emulate a Mealy state machine. Specifically, there is a PLD which has : (1) a programmable logical AND and two programmable logical OR arrays, similar to a field programmable logic array; and (2) one of the two fully programmable OR array generates a next state of the circuit and the second OR array generates an output responsive to both the inputs and the current state.