专利名称 | METHOD AND CIRCUIT FOR NORMALIZING FLOATING POINT | ||
申请号 | JP04216059 | 申请日 | |
公开(公告)号 | JP05216620A | 公开(公告)日 | |
申请(专利权)人 | IBM | 发明人 | FUAREIDON OSUMAN KARIMU; KURISUTOFUAA HANSU ORUSON |
专利来源 | 国家知识产权局 | 转化方式 | |
摘要 |
PURPOSE : To provide a method and circuit for normalizing a floating point by using a register whose width is much smaller than that which is generally necessary for the processing of a data operand. CONSTITUTION : According as the scale of a register 36 is decreased, the number of circuits necessary for normalization is reduced, and a chip area necessary for the execution of an operation is decreased. A normalizing circuit is simplified so that data type whose appearance frequency is high can be efficiently operated by a floating point device. The data type and (or) instructions whose appearance frequency is statistically high necessitate a normalizing function in plural cycles. The width of a required register 36 necessary for the data type and (or) the instructions with high appearance frequency is extremely smaller than that necessary for the data type and (or) the instructions with low appearance frequency. The data are resolved into further smaller parts, and normalized by using the continuos cycles of the normalizing circuit instead of extending the width of the register, and adapting it to such low appearance frequency. |
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