A semiconductor floor plan layout for integrating a Data Dependency Checker (DDC) circuit and a Tag Assignment Logic (TAL) of a Register Renaming Circuit (RRC) circuit to conserve valuable semiconductor real estate. Floor plans of the present invention contemplate laying out the DDC and TAL in such a fashion as to reduce the distance signals must travel between the DDC and TAL, as well as the sitance signals must travel between the TAL and RPM. By rearranging selected DDC comparator rows and their associated TAL, a considerable amount of area can be conserved for performing register renaming for up to eight instructions.