For decreasing the amount of real estate assigned to each memory cell (M21/M22), a random access memory device is fabricated on a semiconductor substrate (21) from a plurality of memory cells each comprising a switching transistor (Sw21 /SW22) and a storage capacitor (STR21 /STR22), wherein the storage capacitor comprises a lower electrode (30a /30b) provided over one of the source and drain regions (23a /23b) of the switching transistor and held in contact therewith, a dielectric film structure (31a /31b) covering the lower electrode, and an upper electrode (32) held in contact with the dielectric film structure and having at least one side edge (36a /36b) substantially self-aligned with one side edge (30aa /30bb) of the lower electrode without any tolerance.