An electrically erasable an programmable read only memory device comprises a plurality of series combinations of memory cells (M111 to M113) arranged in rows and columns, bit lines (Y1) each coupled to the front memory cells of the series combinations in one of the columns, a source line (42e) coupled to the rearmost memory cells of the plurality of series combinations, and word lines (X11 to X13 and Z11 to Z13) associated with the rows of the memory cells, and each of the memory cells is implemented by a parallel combination of a floating gate type field effect transistor (MT) coupled to a first word line (X11 to X13) and a switching transistor (ST) coupled to a second word line (Z11 to Z13) for selectively carrying out a write-in operation without simultaneous erasing operation on the series combination, wherein the floating gate type field effect transistors are formed on the major surface of a semiconductor substrate (41) and the switching transistors are provided over the floating gate type field effect transistor so that the plurality of series combinations occupy a small amount of real estate of the semiconductor substrate in spite of the switching transistors respectively provided for the floating gate type field effect transistors. ;