A CMOS integrated circuit structure with planarized self-aligned transistors and local planarization in the vicinity of the transistors so as to allow an interconnect, with a planar upper surface, which is free of bridging, has good continuity over the planarized topography and is compatible with self-alignment schemes, hence conserving chip real estate. The structure includes self-aligned insulated transistor gates (14a, 14b) and active transistor regions in a substrate (10). A "landing pad" (22) is formed on the substrate (10) at buried contact (44) and polyiso contact locations so as to allow more effective etching at the exact location of the polyiso contact. The integrated circuit structure is locally planarized by formation of an oxide layer (26) and a reflowed overlying glass layer (30) which is etched back to planarize the surface. Using a polyiso mask, portions of the glass layer (30) and underlying oxide (26), landing pad (22), and oxide layers (20) are removed only in the area of the buried contact (44). Then a combined horizontal and vertical interconnect (48a), with a planar upper surface, is formed to electrically connect the buried contact (44) to the gate (14a).