A low power cyclic RSD analog to digital converter (20) has a single RSD stage (22) that receives one of an analog input signal and a residual voltage feedback signal and converts the one selected signal to a digital output signal. The RSD stage (22) generates the residue voltage feedback signal. A first switch (32) is connected between a converter input terminal (30) and an input terminal of the RSD stage (22) for applying the analog input signal to the RSD stage input terminal. A second switch (52) is connected between an output terminal of the RSD stage (22) and the input terminal of the RSD stage. When the first switch (32) is closed, the second switch (52) is open so that the analog input signal is input to the RSD stage (22), and when the first switch (32) is open, the second switch (52) is closed so that the residual voltage feedback signal is input to the RSD stage (22). The RSD stage (22) includes a pair of comparators (34, 36) that compare the selected one of the analog input signal and the residual voltage feedback signal to predetermined high and low voltages, respectively. A logic circuit (38) connected to the comparators (34, 36) receives their outputs and generates the digital output signal based on these outputs. Use of a single stage and only two comparators conserves chip real estate.